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rev 0.4 1mx36 & 2mx18 sram - 1 - jun. 2003 K7D321874A k7d323674a advance document title 32m ddr synchronous sram revision history the attached data sheets are prepared and approved by samsung electronics. samsung electronics co., ltd. reserve the right to change the specifications. samsung electronics will evaluate and reply to your requests and questions on the parameters of this device. if you have any questions, please contact the samsung branch office near your office, call or cortact headquart ers. rev no. rev. 0.0 rev. 0.1 rev 0.2 remark advance advance advance history initial document. remove /g operation thru the spec. - remove /g from punctional block diagram, pin configura- tion, truth table and timing waveforms add 300mhz speed bin. - add part id at ordering information & i dd30 at dc characteris- tics change i li and i lo at dc charcateristics - i li : min -1 -> -3, max 1 -> 3, i lo : min -1 -> -5, max 1 -> 5 change the comment of programmable impedance output driver. change recommended dc operating conditions. - v ref : min 0.68 -> 0.65, max 1.0 -> 0.85 change pin capacitance : c in : 3 -> 3.1 change ac test conditions : t r /r f : 0.4/0.4 -> 0.5/0.5 change ac timing characteristics - t chcl : t khkl -0.1 -> t khkl -0.2 , t clch : t klkh -0.1 -> t klkh -0.2 - t cxcv : 2.10 -> 2.30 change vddq range - in features : 1.5v v ddq -> 1.5~.1.8v v ddq - in recomended dc operating conditions : max v ddq : 1.6 -> 1.9 change truth table : remove clock stop change dc characteristics - x36 i dd : i dd50 : 950 -> 1050, i dd45 : 850 -> 950, i dd40 : 800 -> 860, i dd30 : 750 -> 760 - x18 i dd : i dd50 : 850 -> 1000, i dd45 : 800 -> 900, i dd40 : 750 -> 810, i dd30 : 700 -> 710 - i sb1 : 150 -> 200 change pin capacitance : c in : 3.1 -> 3.2, c out : 4 -> 4.2 change ac timing characteristics - min t khkl, t khkl : -40 : 1.1 -> 1.2, -30 : 1.1 -> 1.4 - min t avkh, t bvkh, t khax, t khbx : -45 : 0.25 -> 0.27 - t kxcv min/max : 0.8/2.3 -> 1.0/2.5 change package thermal characteristics draft data dec. 2002 jan. 2003 feb. 2003 pre- publication draft subject to change without notice
rev 0.4 1mx36 & 2mx18 sram - 2 - jun. 2003 K7D321874A k7d323674a advance revision history rev no. rev 0.3 rev 0.4 remark advance advance history change dc characteristics - x36 i dd : i dd50 : 1050 -> 1150 , i dd45 : 950 -> 1050, i dd40 : 860 -> 960, i dd30 : 760 -> 860 - x18 i dd : i dd50 : 1000 -> 1100, i dd45 : 900 -> 1000, i dd40 : 810 -> 910, i dd30 : 710 -> 810 - i sb1 : 200 -> 300 change 300mhz speed bin to 333mhz draft data may. 2003 jun. 2003
rev 0.4 1mx36 & 2mx18 sram - 3 - jun. 2003 K7D321874A k7d323674a advance ordering information part number organization maximum frequency k7d323674a-hc50 1mx36 500mhz k7d323674a-hc45 450mhz k7d323674a-hc40 400mhz k7d323674a-hc33 333mhz K7D321874A-hc50 2mx18 500mhz K7D321874A-hc45 450mhz K7D321874A-hc40 400mhz K7D321874A-hc33 333mhz general description the k7d323674a and K7D321874A are 37,748,736 bit synchronous pipeline burst mode sram devices. they are organized as 1,048,576 words by 36 bits for k7d323674a and 2,097,152 words by 18 bits for K7D321874A, fabricated using samsung's advanced cmos technology. single differential hstl level clock, k and k are used to initiate the read/write operation and all internal operations are self-timed. at the rising edge of k clock, all addresses and burst control inputs are registered internally. data inputs are registered one cy cle after write addresses are asserted(late write), at the rising edge of k clock for single data rate (sdr) write operations and at risin g and falling edge of k clock for a double data rate (ddr) write operations. data outputs are updated from output registers off the rising edges of k clock for sdr read operations and off the rising and fa lling edges of k clock for ddr read operations. free running echo clocks are supported which are representative of data output access time for all sdr and ddr operations. the chip is operated with 1.8~2.5v power supply and is compatible with hstl input and output. the package is 9x17(153) ball gri d array balls on a 1.27mm pitch. features ? 1mx36 or 2mx18 organizations. ? 1.8~2.5v v dd /1.5v ~1.8v ddq . ? hstl input and outputs. ? single differential hstl clock. ? synchronous pipeline mode of operation with self-timed late write. ? free running active high and active low echo clock output pin. ? registered addresses, burst control and data inputs. ? registered outputs. ? double and single data rate burst read and write. ? burst count controllable with max burst length of 4 ? interleved and linear burst mode support ? bypass operation support ? programmable impedance output drivers. ? jtag boundary scan (subset of ieee std. 1149.1) ? 153(9x17) flip chip ball grid array package(14mmx22mm)
rev 0.4 1mx36 & 2mx18 sram - 4 - jun. 2003 K7D321874A k7d323674a advance functional block diagram k, k b 1 b 3 b 2 register ce memory array 1mx36 data out data in advance control sd/ dd co clock synchronous buffer internal clock generator ce r/ w ld data output strobe data output enable state machine strobe_out s/a array 2 : 1 mux data in register write buffer w/d array echo clock output 36(or 18)x2 36(or 18)x2 36(or18)x2 36(or18)x2 xdin cq, cq dq 36(or 18) select & r/ w control output buffer write ce burst counter register address address comparator 2:1 mux dec. 20(or 21) 18(or 19) 18(or 19) 20(or 21) (burst write sa[0:20]( or sa[0:21]) or (2mx18) (2 stage) (2 stage) (burst address) address) pin description pin name pin description pin name pin description k, k differential clocks tck jtag test clock sa synchronous address input tms jtag test mode select sa 0 , sa 1 synchronous burst address input (sa 0 = lsb) tdi jtag test data input dq synchronous data i/o tdo jtag test data output cq, cq differential output echo clocks v ref hstl input reference voltage b 1 load external address v dd power supply b 2 burst r/ w enable v ddq output power supply b 3 single/double data selection v ss gnd lbo linear burst order nc no connection zq output driver impedance control input
rev 0.4 1mx36 & 2mx18 sram - 5 - jun. 2003 K7D321874A k7d323674a advance package pin configurations (top view) k7d323674a(1mx36) 1 2 3 4 5 6 7 8 9 a v ss v ddq sa sa zq sa sa v ddq v ss b dq 20 dq 19 sa v ss b 1 v ss sa dq 16 dq 15 c v ss v ddq sa sa sa sa sa v ddq v ss d dq 30 dq 28 sa v ss (5) v dd v ss (6) sa dq 7 dq 5 e v ss v ddq v ss v dd v ref v dd v ss v ddq v ss f dq 21 cq dq 18 v dd v dd v dd dq 17 cq dq 14 g v ss v ddq v ss v ss k v ss v ss v ddq v ss h dq 31 dq 29 dq 27 v dd k v dd dq 8 dq 6 dq 4 j v ss v ddq v ss v dd v dd v dd v ss v ddq v ss k dq 22 dq 24 dq 26 v ss b 2 v ss dq 9 dq 11 dq 13 l v ss v ddq v ss lbo (7) b 3 mode(9) v ss v ddq v ss m dq 32 cq dq 35 v dd v dd v dd dq 0 cq dq 3 n v ss v ddq v ss v dd v ref v dd v ss v ddq v ss p dq 23 dq 25 nc * v ss v dd (2) v ss sa dq 10 dq 12 r v ss v ddq v dd (4) sa sa 1 sa v dd (3) v ddq v ss t dq 33 dq 34 sa v ss sa 0 v ss sa dq 1 dq 2 u v ss v ddq tms tdi tck tdo nc(8) v ddq v ss K7D321874A(2mx18) (1) variable address see "variable address assignment table" (2) variable address see "variable address assignment table" (3) variable address see "variable address assignment table" (4) variable address see "variable address assignment table" (5) variable address see "variable address assignment table" (6) variable address see "variable address assignment table" (7) lbo for ddr1, m 2 for ddr3 (8) nc for ddr1, zt for ddr3 (9) internally nc since ddr2 is not supported 1 2 3 4 5 6 7 8 9 a v ss v ddq sa sa zq sa sa v ddq v ss b nc dq 10 sa v ss b 1 v ss sa nc dq 5 c v ss v ddq sa sa sa sa sa v ddq v ss d dq 11 nc sa v ss (5) v dd v ss (6) sa dq 7 nc e v ss v ddq v ss v dd v ref v dd v ss v ddq v ss f nc cq nc v dd v dd v dd dq 8 nc dq 4 g v ss v ddq v ss v ss k v ss v ss v ddq v ss h dq 12 nc dq 9 v dd k v dd nc dq 6 nc j v ss v ddq v ss v dd v dd v dd v ss v ddq v ss k nc dq 15 nc v ss b 2 v ss dq 0 nc dq 3 l v ss v ddq v ss lbo (7) b 3 mode(9) v ss v ddq v ss m dq 13 nc dq 17 v dd v dd v dd nc cq nc n v ss v ddq v ss v dd v ref v dd v ss v ddq v ss p nc dq 16 sa v ss v dd (2) v ss sa nc dq 2 r v ss v ddq v dd (4) sa sa 1 sa v dd (3) v ddq v ss t dq 14 nc sa v ss sa 0 v ss sa dq 1 nc u v ss v ddq tms tdi tck tdo nc(8) v ddq v ss
rev 0.4 1mx36 & 2mx18 sram - 6 - jun. 2003 K7D321874A k7d323674a advance variable address assignment table note : - sram density definition beyond 144mb will include the parity bits. density ball 5c (1) ball 5p (2) ball 7r (3) ball 3r (4) ball 4d (5) ball 6d (6) 32 mb sa v dd v dd v dd v ss v ss 64 mb sa sa v dd v dd v ss v ss 144 mb nc sa sa sa v ss v ss 288 mb sa sa sa sa v ss v ss 576 mb nc sa sa sa sa sa 1152 mb sa sa sa sa sa sa
rev 0.4 1mx36 & 2mx18 sram - 7 - jun. 2003 K7D321874A k7d323674a advance read operation(single and double) during sdr read operations, addresses and controls are registered at the first rising edge of k clock and then the internal arra y is read between first and second rising edges of k clock. data outputs are updated from output registers off the second rising edge of k clock. during ddr read operations, addresses and controls are registered at the first rising edge of k clock, and then the int ernal array is read twice between first and second rising edges of k clock. data outputs are updated from output registers sequential ly by burst order off the second rising and falling edge of k clock. interleave and linear burst operation is controlled by lbo pin and the burst count is controllable with the maximum burst length of 4. to avoid data contention,at least one nop operations are required between the last read and the first write operation. write operation(late write) during sdr write operations, addresses and controls are registered at the first rising edge of k clock and data inputs are regis tered at the following rising edge of k clock. during ddr write operations, addresses and controls are registered at the first rising edge of k clock and data inputs are registered twice at the following rising and falling edge of k clock. write addresses and data input s are stored in the data in registers until the next write operation, and only at the next write opeation are data inputs fully writte n into sram array. e cho clock operation free running type of echo clocks are generated from k clock regardless of read, write and nop operations. they will stop operati on only when k clock is in the stop mode. echo clocks are designed to represent data output access time and this allows the echo clocks to be used as reference to capture data outputs outputs. bypass read operation bypass read operation occurs when the last write operation is followed by a read operation where write and read addresses are identical. for this case, data outputs are from the data in registers instead of sram array. programmable impedance output driver the data output and echo clock driver impedance are adjusted by an external resistor, rq, connected between zq pin and v ss , and are equal to rq/5. for example, 250 w resistor will give an output impedance of 50 w . output driver impedance tolerance is 15% by test(10% by design) and is periodically readjusted to reflect the changes in supply voltage and temperature. output driver imped - ance is updated every 64 clock cycles of non-read operation (write or nop) but since the echo clock drivers are in operation eve n during non-read operation, the impedance is update only the drivers are not in operation. therefore impedance updates for "0s" o r pull down drivers occur whenever the echo clock driver is driving "1s" or vice versa. furthermore, to guarantee optimum output driver impedance after power up, the sram need 2048 deselect (or write) cycles.
rev 0.4 1mx36 & 2mx18 sram - 8 - jun. 2003 K7D321874A k7d323674a advance truth table note : - b(both) is din in write cycle and dout in read cycle. byte write function is not supported. x means "don't care". - k & k are complementary. k b1 b2 b3 dq operation - h l x hi-z no operation, pipeline high-z - l h h dout load address, single read - l h l dout load address, double read - l l h din load address, single write - l l l din load address, double write - h h x b increment address, continue 4 burst operation for interleaved burst ( lbo = v ddq ) note : - for interleave burst lbo = v ddq is recommended. if lbo = v dd , it must not exceed 2.63v. interleaved burst case 1 case 2 case 3 case 4 a 1 a 0 a 1 a 0 a 1 a 0 a 1 a 0 first address fourth address 0 0 1 1 0 1 0 1 0 0 1 1 1 0 1 0 1 1 0 0 0 1 0 1 1 1 0 0 1 0 1 0 burst sequence table 4 burst operation for linear burst ( lbo = v ss ) linear burst mode case 1 case 2 case 3 case 4 a 1 a 0 a 1 a 0 a 1 a 0 a 1 a 0 first address fourth address 0 0 1 1 0 1 0 1 0 1 1 0 1 0 1 0 1 1 0 0 0 1 0 1 1 0 0 1 1 0 1 0
rev 0.4 1mx36 & 2mx18 sram - 9 - jun. 2003 K7D321874A k7d323674a advance note : 1. state transitions ; b 1 =(load address), b 1 =(increment address, continue) b 2 =(read), b 2 =(write) b 3 =(single data rate), b 3 =(double data rate) bus cycle state diagram load new address increment address increment address increment address increment address read sdr write sdr read ddr write ddr b 2 , b 3 b 1 , b 2 b 1 , b 2 b 1 , b 2 b 1 , b 2 b 1 , b 2 b 1 , b 2 b 1 , b 2 b 1 , b 2 no op power up b 2 , b 3 b 1 b 2 , b 3 b 1 b 2 , b 3 b 1 b 1 b 1 , b 2 b 1 , b 2 b 1 , b 2 b 1 , b 2 b 1 , b 2 b 1 , b 2 b 1 , b 2 b 1 , b 2
rev 0.4 1mx36 & 2mx18 sram - 10 jun. 2003 K7D321874A k7d323674a advance recommended dc operating conditions note :1. these are dc test criteria. dc design criteria is v ref 50mv. the ac v ih /v il levels are defined separately for measuring timing parameters. 2. v ih (max)dc= v ddq +0.3, v ih (max)ac= 2.6 v (2.1v for dqs) (pulse width 20% of cycle time). 3. v il (min)dc= - 0.3v, v il (min)ac=-1.0v (-0.5v for dqs) (pulse width 20% of cycle time). parameter symbol min typ max unit note core power supply voltage v dd 1.7 2.5 2.6 v output power supply voltage v ddq 1.4 1.5 1.9 v input high level voltage v ih v ref +0.1 - v ddq +0.3 v 1, 2 input low level voltage v il -0.3 - v ref -0.1 v 1, 3 input reference voltage v ref 0.68 0.75 1.0 v absolute maximum ratings note : power dissipation capability will be dependent upon package characteristics and use environment. see enclosed thermal impedan ce data. stresses greater than those listed under " absolute maximum ratings" may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. parameter symbol value unit core supply voltage relative to v ss v dd -0.5 to 3.13 v output supply voltage relative to v ss v ddq -0.5 to 2.3 v voltage on any pin relative to v ss v in -0.5 to v ddq +0.5 (2.3v max ) v output short-circuit current(per i/o) i out 25 ma storage temperature t str -55 to 125 c maxmum junction temperature t j 110 c maxmum power dissipation p d 3.0 w dc characteristics note :1. minimum cycle. i out =0ma. 2. 50% read cycles. 3. |i oh |=(v ddq /2)/(rq/5) 15% @v oh =v ddq /2 for 175 w rq 300 w . 4. |i ol |=(v ddq /2)/(rq/5) 15% @v ol =v ddq /2 for 175 w rq 300 w . parameter symbol min max unit note average power supply operating current(x36) (cycle time = t khkh min) i dd50 i dd45 i dd40 i dd33 - 1150 1050 960 900 ma 1,2 average power supply operating current(x18) (cycle time = t khkh min) i dd50 i dd45 i dd40 i dd33 - 1100 1000 910 850 ma 1,2 stop clock standby current (v in =v dd -0.2v or 0.2v fixed, k=low, k =high) i sb1 - 300 ma 1 input leakage current (v in =v ss or v ddq ) i li -3 3 m a output leakage current (v out =v ss or v ddq ) i lo -5 5 m a output high voltage(programmable impedance mode) v oh1 v ddq /2 v ddq v 3 output low voltage(programmable impedance mode) v ol1 v ss v ddq /2 v 4 output high voltage(i oh =-0.1ma) v oh2 v ddq -0.2 v ddq v output low voltage(i ol =0.1ma) v ol2 v ss 0.2 v
rev 0.4 1mx36 & 2mx18 sram - 11 jun. 2003 K7D321874A k7d323674a advance pin capacitance note : periodically sampled and not 100% tested.(t a =25 c , f=500mhz) parameter symbol test condition typ max unit input capacitance c in v in =0v - 3.2 pf data output capacitance c out v out =0v - 4.2 pf ac test conditions (t a =0 to 70 c , v dd =2.37 -2.63v, v ddq =1.5v) parameter symbol value unit note input high/low level v ih /v il 1.25/0.25 v - input reference level v ref 0.75 v - input rise/fall time t r /t f 0.5/0.5 ns - output timing reference level 0.75 v - clock input timing reference level cross point v - output load see below - 50 w 50 w ac test output load 25 w 5 pf dq 0.75v 5 pf 0.75v 50 w 50 w 0.75v
rev 0.4 1mx36 & 2mx18 sram - 12 jun. 2003 K7D321874A k7d323674a advance ac timing characteristics notes : 1. the maximum cycle time must be limited to guarantee ac timing specification. 2. this parameter is guaranteed by design, and may not be tested at values shown in the table. 3. this parameter refers to cq and cq rising and falling edges. 4. this parameter is only for 32mb density 5. k and k clocks must be used differencitally to meet ac timing specifications. parameter symbol -50 -45 -40 -33 units notes min max min max min max min max clock clock cycle time t khkh 2.00 4.00 2.20 4.40 2.50 5.00 3.00 6.00 ns 1 clock high pulse width t khkl 0.90 1.00 1.20 1.40 ns clock low pulse width t klkh 0.90 1.00 1.20 1.40 ns setup times address setup time t avkh 0.25 0.27 0.30 0.30 ns control(b1,b2,b3) setup time t bvkh 0.25 0.27 0.30 0.30 ns data setup time t dvkx 0.17 0.20 0.20 0.20 ns 2 hold times address hold time t khax 0.25 0.27 0.30 0.30 ns control(b1,b2,b3) hold time t khbx 0.25 0.27 0.30 0.30 ns data hold time t kxdx 0.17 0.20 0.20 0.20 ns 2 output times echo clock high pulse width t chcl t khkl -0.2 t khkl +0.2 t khkl -0.2 t khkl +0.2 t khkl -0.2 t khkl +0.2 t khkl -0.2 t khkl +0.2 ns 2 echo clock low pulse width t clch t klkh -0.2 t klkh +0.2 t klkh -0.2 t klkh +0.2 t klkh -0.2 t klkh +0.2 t klkh -0.2 t klkh +0.2 ns 2 clock to echo clock valid t kxcv 1.00 2.50 1.00 2.50 1.00 2.50 1.00 2.50 ns data output tracking t qtrk -0.20 0.20 -0.20 0.20 -0.20 0.20 -0.20 0.20 ns 2,3
rev 0.4 1mx36 & 2mx18 sram - 13 jun. 2003 K7D321874A k7d323674a advance nop continue k k b1 sa t avkh t khax cq nop 1 2 3 4 5 6 7 8 10 12 11 b2 b3 cq dq read (burst of 4) read (burst of 2) read (burst of 4) nop write continue write (burst of 4) read 9 continue read read (burst of 4) continue read a 0 a 1 a 2 a 3 q x2 q 01 q 02 q 03 q 04 q 51 q 52 q 53 q 54 q 11 q 12 d 21 d 23 d 24 d 22 q 31 t bvkh t khbx t chqz t kxch t chlz t chqv t chqx t dvkh t khdx t khkh undefined don ? t care a 5 note 1. q 01 refers to output from address a. q 02 refers to output from the next internal burst address following a, etc. 2. outputs are disabled(high-z) one clock cycle after nop detected or after no pending data requests are present. 3. doing more than one read continue or write continue will cause the address to wrap around. timing waveforms for double data rate cycles (burst length=4, 2)
rev 0.4 1mx36 & 2mx18 sram - 14 jun. 2003 K7D321874A k7d323674a advance timing waveforms for single data rate cycles note : 1. q 01 refers to output from address a 0 . q 02 refers to output from the next internal burst address following a 0 , etc. 2. outputs are disabled(high-z) one clock cycle after nop detected or after no pending data requests are present. 3. this devices supports cycle lengths of 1, 2, 4. continue(b1=high, b2=high, b3=x) up to three times following a b1 operation. any further continue assertions constitute invalid operations. 4. this device will have an address wraparound if further continues are applied. nop continue t khkh t avkh t khax nop 1 2 3 4 5 6 7 8 10 12 11 read (burst of 2) read read (burst of 4) nop write continue write (burst of 2) read 9 continue read continue read continue read a 0 a 1 a 2 a 3 q x1 d 22 d 21 t bvkh t khbx t chqz t kxch t chlz t chqv t chqx t dvkh t khdx t klkh q 31 q 01 q 02 q 03 q 04 q 11 undefined don ? t care t khkl k k b1 sa b2 b3 dq cq cq (burst length=4, 2, 1) (burst of 1)
rev 0.4 1mx36 & 2mx18 sram - 15 jun. 2003 K7D321874A k7d323674a advance ieee 1149.1 test access port and boundary scan-jtag tap controller state diagram jtag block diagram sram core bypass reg. identification reg. instruction reg. control signals tap controller tdo sa sa tdi tms tck test logic reset run test idle 0 1 1 1 1 0 0 0 1 0 1 1 0 0 0 1 0 1 1 1 0 0 0 0 0 0 0 select dr capture dr shift dr exit1 dr pause dr exit2 dr update dr select ir capture ir shift ir exit1 ir pause ir exit2 ir update ir 1 1 1 1 1 the sram provides a limited set of ieee standard 1149.1 jtag functions. this is to test the connectivity during manufacturing between sram, printed circuit board and other components. internal data is not driven out of sram under jtag control. in conform - ance with ieee 1149.1, the sram contains a tap controller, instruction register, bypass register and id register. the tap contro l- ler has a standard 16-state machine that resets internally upon power-up, therefore, trst signal is not required. it is possible to use this device without utilizing the tap. to disable the tap controller without interfacing with normal operation of the sram, tck must be tied to v ss to preclude mid level input. tms and tdi are designed so an undriven input will produce a response identical to the application of a logic 1, and therefore can be left unconnected. but they may also be tied to v dd through a resistor. tdo should be left unconnected. jtag instruction coding note : 1. places dqs in hi-z in order to sample all input data regardless of other sram inputs. input terminators are switched off. 2. tdi is sampled as an input to the first id register to allow for the serial shift of the external tdi data. 3. bypass register is initiated to v ss when bypass instruction is invoked. the bypass register also holds serially loaded tdi when exiting the shift dr states. 4. sample instruction dose not places dqs in hi-z. 5. private1 and private2 are reserved for the exclusive use of sam- sung. this instruction should not be used. ir2 ir1 ir0 instruction tdo output notes 0 0 0 extest boundary scan register 1 0 0 1 idcode identification register 2 0 1 0 sample-z boundary scan register 1 0 1 1 private3 bypass register 3,5 1 0 0 sample boundary scan register 4 1 0 1 private2 bypass register 3,5 1 1 0 private1 bypass register 3,5 1 1 1 bypass bypass register 3
rev 0.4 1mx36 & 2mx18 sram - 16 jun. 2003 K7D321874A k7d323674a advance boundary scan exit order(x36) * reserved for mode pin 1 5p v dd (2) 38 5c sa 2 5r sa 1 39 4a sa 3 5t sa 0 40 4c sa 4 6r sa 41 4d v ss (2 5 7t sa 42 3a sa 6 7r v dd (2) 43 3b sa 7 7p sa 44 3c sa 8 8t dq1 45 3d sa 9 9t dq2 46 2b dq19 10 8p dq10 47 1b dq20 11 7m dq0 48 2d dq28 12 9p dq12 49 3f dq18 13 8m cq (3) 50 1d dq30 14 9m dq3 51 2f cq(3) 15 7k dq9 52 1f dq21 16 8k dq11 53 3h dq27 17 9k dq13 54 2h dq29 18 6l mode 55 1h dq31 19 5h k 56 5a zq(1) 20 5g k 57 5b b 1 21 9h dq4 58 5k b 2 22 8h dq6 59 5l b 3 23 7h dq8 60 4l lbo 24 9f dq14 61 1k dq22 25 8f cq(3) 62 2k dq24 26 9d dq5 63 3k dq26 27 7f dq17 64 1m dq32 28 8d dq7 65 2m cq (3) 29 9b dq15 66 1p dq23 30 8b dq16 67 3m dq35 31 7d sa 68 2p dq25 32 7c sa 69 1t dq33 33 7b sa 70 2t dq34 34 7a sa 71 3r v dd (2) 35 6d v ss (2) 72 3t sa 36 6c sa 73 4r sa 37 6a sa 74 7u nc boundary scan exit order(x18) * reserved for mode pin 1 5p v dd (2) 28 5c sa 2 5r sa 1 29 4a sa 3 5t sa 0 30 4c sa 4 6r sa 31 4d v ss (2) 5 7t sa 32 3a sa 6 7r v dd (2) 33 3b sa 7 7p sa 34 3c sa 8 8t dq1 35 3d sa 36 2b dq10 9 9p dq2 10 8m cq (3) 37 1d dq11 38 2f cq(3) 11 7k dq0 39 3h dq9 12 9k dq3 13 6l mode 40 1h dq12 14 5h k 41 5a zq(1) 15 5g k 42 5b b1 43 5k b2 16 8h dq6 44 5l b3 45 4l lbo 17 9f dq4 46 2k dq15 18 7f dq8 47 1m dq13 19 8d dq7 20 9b dq5 48 3m dq17 21 7d sa 49 2p dq16 22 7c sa 50 1t dq14 23 7b sa 51 3p sa 24 7a sa 52 3r v dd (2) 25 6d v ss (2) 53 3t sa 26 6c sa 54 4r sa 27 6a sa 55 7u nc note : 1. if pin is connected as they should, tdo will be low. if pin is open, tdo will be high 2. this pin is place holder for higher density. tdo will be low for v ss and high for v dd 3. cq and cq are outputs during boundary scan. cq reflects the input to k and cq outputs the inverted value of k. it is prohibited to force cq and cq . and tdo is ?x?.(don?t care) scan register definition part instruction register bypass register id register boundary scan 1m x 36 3 bits 1 bits 32 bits 74 bits 2m x 18 3 bits 1 bits 32 bits 55 bits
rev 0.4 1mx36 & 2mx18 sram - 17 jun. 2003 K7D321874A k7d323674a advance jtag dc operating conditions note : 1. the input level of sram pin is to follow the sram dc specification. parameter symbol min typ max unit note power supply voltage v dd 1.7 2.5 2.6 v input high level v ih 0.65*v dd - v dd +0.3 v input low level v il -0.3 - 0.35*v dd v output high voltage(i oh =-2ma) v oh 0.75*v dd - v dd v output low voltage(i ol =2ma) v ol v ss - 0.25*v dd v jtag ac characteristics parameter symbol min max unit note tck cycle time t chch 50 - ns tck high pulse width t chcl 20 - ns tck low pulse width t clch 20 - ns tms input setup time t mvch 5 - ns tms input hold time t chmx 5 - ns tdi input setup time t dvch 5 - ns tdi input hold time t chdx 5 - ns clock low to output valid t clqv 0 10 ns jtag ac test conditions note : 1. see sram ac test output load on page 5. parameter symbol min unit note input high/low level v ih /v il v dd /0.0 v input rise/fall time tr/tf 1.0/1.0 ns input and output timing reference level v dd /2 v 1 jtag timing diagram tck tms tdi tdo t chch t chcl t clch t mvch t chmx t dvch t chdx t clqv id register definition part revision number (31:28) part configuration (27:18) vendor definition (17:12) samsung jedec code (11: 1) start bit (0) 1m x 36 0000 01000 00100 xxxxxx 00001001110 1 2m x 18 0000 01001 00011 xxxxxx 00001001110 1
rev 0.4 1mx36 & 2mx18 sram - 18 jun. 2003 K7D321874A k7d323674a advance 153 bga package thermal characteristics note : 1. junction temperature can be calculated by : t j = t a + p d x q ja or t j = t c + p d x q jc 2. strongly recommends using a heat sink because it greatly improves the ambient temperature requirement parameter symbol thermal resistance unit note junction to case q jc 0.9 c /w junction to board q jb 6.9 c /w junction to ambient(at air flow of 1m/sec) q ja 16.1 c /w junction to ambient(at still air) q ja 19.5 c /w package dimensions 153-fcbga-14.00x22.00 lid units:millimeters/inches 1 . 2 7 0 b s c ? bottom view 0.300 max m 153- ? 0.760 0.150 12.000 2 2 . 0 0 0 1.27x8=10.160 top view 0.150 max 1 . 2 7 x 1 6 = 2 0 . 3 2 0 1.270 bsc 1 1 . 0 0 0 7.000 #a1 underfill 0 . 6 0 0 2 . 7 5 0 1 . 2 0 0 underfill b c d e f g h j k l m n p r t u a 2 0 . 0 0 0 metal lid 14.000 0.750 min 0 . 7 5 0 m i n 1 0 . 1 6 0 5.080 0 . 2 0 0 2 2 . 0 0 0 #a1 index a b 14.000 (datum a) (datum b) 7 6 5 4 3 2 1 9 8

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